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Keywords: RTL/Logic Design Engineer, Location: Santa Clara, CA

Page: 3

Product Engineer - Tessent DFT

as Product Engineer, specializing in design-for-test (DFT). Tessent is the market and technology leader of automated tools... delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design...

Company: Siemens
Location: Santa Clara, CA
Posted Date: 12 Dec 2025
Salary: $129600 - 233300 per year

Mixed Signal Model Verification Engineer

. Strong understanding of custom circuit schematic. Strong background in analog integrated circuit design. Proficiency in RTL design... mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number. It...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 05 Dec 2025

Mixed Signal Model Verification Engineer

in RTL design languages like SystemVerilog Experience with formal equivalence checking tools like ESP We are seeking... a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real...

Company: LanceSoft
Location: Santa Clara, CA
Posted Date: 04 Dec 2025

Formal Verification Engineer - New College Grad 2026

-on experience with HDLs such as Verilog / System Verilog. Ability to understand RTL quickly. Understanding of temporal logic...As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $108000 - 184000 per year

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality. • Build and Test Infrastructure: Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

CPU Implementation Engineer

-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis... and 3+ years of relevant industry experience Experience in logic design and digital circuits Experience with TCL or Perl...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

SR FPGA/CPLD Engineer

Knowledge: Write and maintain RTL using Verilog to implement complex digital logic Need work in lab to validate the design... and collaboration with system engineer Need have good knowledge of various IP to be integrated into the design. Collaborate...

Posted Date: 05 Nov 2025

Senior DFT Engineer

vendor tools Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure... , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

CPU Processor Power Management Verification Engineer

with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

CPU Gate Level Synthesis Engineer

/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions • Early stage power... design, RTL synthesis, and physical design Preferred Qualifications The ideal candidate should ideally possess CPU...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL... Experience with digital logic design, test/debug feature, or DFT architecture Experience with DFT and structural debug concepts...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Processor Power Management Verification Engineer

with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL... of digital logic design, debug feature, and DFT architecture and microarchitecture Proficiency in programming and scripting...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

CPU Processor Power Management Verification Engineer

with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Senior DFX Methodology Engineer

to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade...We are now looking for a Senior DFT Engineer! NVIDIA has continuously reinvented itself over two decades...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Oct 2025

CPU Silicon Validation Engineer

functional validation of our CPUs, with the aim of identifying logic design and circuit bugs. You will be developing CPU test... understanding of the logic design and verification process Background in silicon bring-up and system debug experience...

Company: Apple
Location: Santa Clara, CA
Posted Date: 23 Oct 2025
Salary: $126800 - 190900 per year

Senior DFX Methodology Engineer

vendor tools Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure...We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Oct 2025

Senior DFT Methodology Engineer

with 2+ years of experience in DFT, system architecture, or RTL design. Understanding of fundamental DFT topics.... Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power. Strong programming...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Oct 2025

Senior Formal Verification Engineer

NVIDIA is looking for Formal Verification Engineer to help verify the design and implementation of industry’s leading...-on experience with Verilog / System Verilog HDLs, temporal logic assertions, and able to understand complex RTL quickly. Excellent...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 16 Oct 2025

Senior Reset and Boot ASIC Engineer

. You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. Integrate modules into the overall SOC... of system-level functions like Reset or Chip Boot Solid frontend ASIC design skills, including RTL design, asynchronous...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 01 Oct 2025