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Keywords: Senior Formal Verification Engineer, Location: Santa Clara, CA

Page: 1

Senior Formal Verification Engineer

to do their best work. Come join the team and see how you can make a lasting impact on the world. As a Formal Verification Engineer... will be to verify the micro-architecture using formal verification tools, define the verification scope, and ensure correctness...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Nov 2025

Senior Formal Verification Engineer

NVIDIA is looking for Formal Verification Engineer to help verify the design and implementation of industry’s leading... CPUs and other High Performance Computing Solutions. As a Formal Verification Engineer, you will play a key role...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

Senior Design Verification Engineer

Job Details: Job Description: Intel is seeking a highly technical Senior Design Verification Engineer... innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows...

Company: Intel
Location: Santa Clara, CA
Posted Date: 08 Jan 2026

Senior ASIC Design Verification Engineer

NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world... verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 18 Dec 2025

Senior ASIC Verification Engineer

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience... verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc. Exposure on block level and system-level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Senior Design Verification Engineer

simulations, formal verification, HW/SW reuse and simulation performance. Work with cross functional IP teams for Integration... ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 14 Nov 2025
Salary: $126700 - 190100 per year

Senior ASIC Design Engineer, Memory Controller

NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll... including functional and formal verification, emulation, synthesis & timing analysis, power estimation and ECO...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Dec 2025

Senior ASIC Design Engineer

NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design..., you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior System Software Engineer - QNX BSP and IO Virtualization

We have an exciting opportunity for a talented Senior System Software Engineer to join our dynamic Automotive Team... hands-on experience in Ada/SPARK programming (including specification and formal verification) and TLA+ formal verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Dec 2025

Senior ASIC Design Engineer

We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA.... Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior ASIC Design Engineer - DFX

We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades.... Strong proficiency in micro-architecture and RTL development using Verilog. Experience with formal verification using JasperGold...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Oct 2025

Senior Principal Engineer, Physical Design

/crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), formal or physical verification (Formality... Expect As a senior leader in the central physical design team, you will: Shape the long-term vision for physical design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Dec 2025

Senior ASIC Design Engineer (NetSec)

, emulation, formal methods, and silicon bring-up. Collaborate with verification engineers to debug complex scenarios, close... 802.3), or search-algorithm accelerators. Formal-verification ownership. Hands-on silicon validation and lab bring-up. Additional...

Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Senior ASIC Design Engineer (NetSec)

, emulation, formal methods, and silicon bring-up. Collaborate with verification engineers to debug complex scenarios, close... 802.3), or search-algorithm accelerators. Formal-verification ownership. Hands-on silicon validation and lab bring-up. Additional...

Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Senior Staff Engineer, Physical Design

of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous Experience with multi... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Engineer, Physical Design

analysis tools like Voltus or PrimeRail is advantageous Working knowledge of physical verification and formal verification...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Senior Staff FPGA/Firmware Design Engineer

. Contribute to formal design processes, including requirements management and documentation. What We're Looking For Bachelor... or similar field. Proficiency in FPGA architecture, design, modelling, simulation, and verification. Expertise in Verilog...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $121400 - 181800 per year

Senior Principal Digital IC Design Engineer

, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification..., accelerators, and subsystems. Work closely with the architecture, floor planning, backend, verification, DFT, STA teams...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Lead Electronics & Semiconductor Engineer

are the same. Senior Manager 2 - Lead Electronics and Semiconductor Engineer About the Role Join our Center...). Strong grasp of functional coverage, simulation, emulation, and formal verification. Proven ability to lead teams, influence...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 11 Jan 2026
Salary: $105600 - 197175 per year

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year