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Keywords: RTL Design Engineer, Location: Santa Clara, CA

Page: 1

RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware...: Microarchitectural design and RTL implementation of IP features. PHY Digital Architecture development from pathfinding, coding...

Posted Date: 12 Jun 2025

RTL Design Engineer

, Performance and Area while driving schedule and quality. We are looking for an experienced, conscientious logic design engineer... architectural solutions to achieve requirements Perform logic design, Register Transfer Level (RTL) coding for new features...

Posted Date: 29 May 2025

Principal CPU Systems Debug Architecture/RTL Engineer

Engineering General Summary: We are hiring a talented engineer for CPU System Debug Architecture/RTL engineer targeted.... Development, assessment and refinement of RTL design to target power, performance, area and timing goals. ● Functional...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 21 Apr 2025

CPU Systems RTL Engineer

such as Perl or Python. Roles and Responsibilities As an RTL engineer you will own or participate in the following... team execute on the functional verification strategy. ● Performance verification support. Help verify that the RTL design...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 20 Apr 2025

Principal Software Engineer, RTL Optimization Tools

in algorithm development related to graph traversal, pattern matching, and optimization Fluency in RTL design, including Verilog... experience including both software and hardware roles, especially involving SOC/IP integration or RTL design Experience...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Apr 2025

ASIC Design Engineer - New College Grad 2025

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA...-architecture and design including RTL design, synthesis, functional verification and timing analysis using innovative CAD tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 05 Jul 2025

Senior Logic Design Engineer, Cache Coherent Interconnects

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team... performance and low power RTL, Synthesis and Timing closure, and design documentation. Collaborate with our verification team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

ASIC Design Efficiency Engineer - New College Grad 2026

We are now looking for an ASIC Design Efficiency Engineer. NVIDIA is seeking extraordinary methodology engineers...) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Jun 2025
Salary: $96000 - 184000 per year

Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Staff Engineer, Physical Design... semiconductor industry. Your collaboration with the RTL design and global timing teams will ensure smooth end-to-end design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Jun 2025
Salary: $105470 - 158000 per year

Senior Staff Engineer, Physical Design

-outs and help drive Marvell’s continued leadership in the semiconductor industry. Your collaboration with the RTL design..., and physical verification. Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Jun 2025
Salary: $124420 - 186400 per year

Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Silicon Design Engineer to Research, design, develop, and/or test electronic... or skills: Performing hardware verification; ASIC design tools (synthesis, simulation); RTL design or coding; Logic...

Posted Date: 22 Jun 2025

Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Silicon Design Engineer to Research, design, develop, and/or test electronic... or skills: Performing hardware verification; ASIC design tools (synthesis, simulation); RTL design or coding; Logic...

Posted Date: 22 Jun 2025

Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Silicon Design Engineer to Research, design, develop, and/or test electronic... or skills: Performing hardware verification; ASIC design tools (synthesis, simulation); RTL design or coding; Logic...

Posted Date: 21 Jun 2025

ASICS Design Verification Engineer - SCL

of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL. 12+ years of experience... in Engineering, Science, or a closely related field 10+ years of experience with ASIC design and verification tools, techniques...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 19 Jun 2025

ASIC Design Efficiency Engineer

We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers...) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jun 2025

ASIC Design Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL/micro-architecture...

Company: Apple
Location: Santa Clara, CA
Posted Date: 15 Jun 2025

Senior Staff Engineer, Physical Design

-outs and help drive Marvell’s continued leadership in the semiconductor industry. Your collaboration with the RTL design.... Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Jun 2025
Salary: $124420 - 186400 per year

GPU Logic Design Engineer

efficient low latency designs with scalabilities and flexibilities Power and Area efficient RTL logic design and DV support... and system verilog, synthesizable RTL Knowledgeable in modern design techniques and energy-efficient/low power logic design...

Company: Intel
Location: Santa Clara, CA
Posted Date: 08 Jun 2025

ASIC Design Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL/micro-architecture...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Jun 2025

Sr Principal ASIC Design Engineer (NetSec)

and subsystems. Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets... or subsystems from specification through mass production silicon. Expert-level proficiency in SystemVerilog RTL design. Deep...

Location: Santa Clara, CA
Posted Date: 07 Jun 2025