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Keywords: RTL Engineer, Location: Santa Clara, CA

Page: 6

Senior SRAM Circuit Design Engineer

and waveform debugging tools. Write RTL and perform verification against circuit What we need to see: MS in Electrical...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025

ASIC Design Engineer - New College Grad 2026

and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural... trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025
Salary: $96000 - 161000 per year

Physical Design Methodology Engineer

, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve... methodologies. Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop...

Posted Date: 09 Nov 2025

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 05 Nov 2025
Salary: $105000 - 135000 per year

Senior ASIC Engineer

will have: *RTL Design *ASIC front-end experience *Scripting Languages knowledge (e.g. Perl or Python) Minimum Qualifications...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 01 Nov 2025
Salary: $126700 - 190100 per year

Senior Principal Digital IC Design Engineer

. Implement designs using good RTL coding and low power techniques. Collaborate with the backend team to close on synthesis... to be: Fluent in System Verilog RTL coding techniques. Familiar with modern SoC architectures and various interface technologies...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Analog-Mixed Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 22 Oct 2025
Salary: $105000 - 135000 per year

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... and high performance. Knowledge of Cache design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Oct 2025

Senior ASIC Verification Engineer - GPU

future direction of the methodology for the testbench Partner closely with RTL and architecture teams to help refine the...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Oct 2025

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... subsystem Academic experience with RTL/micro-architecture development Good understanding of PPA (performance/power/area...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

AI/ML Design Verification Methodology Lead Engineer

flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 09 Oct 2025

Principal Silicon Design Engineer

team. KEY RESPONSIBILITIES: Integrate AMD internal IPs RTL/DV environments into SoC Debug function/performance... of Graphics, Display, SMU IPs Engage with IP and SOC teams to drive closure to IP RTL deliverables Work with global Front-End...

Posted Date: 20 Sep 2025

Advanced Device Modeling Expert - TCAD

experienced Senior Engineer to join our Advanced Device Modeling team onsite in Santa Clara, CA. This primary responsibility..., RTL synthesis, DRC/LVS and place-and-route and timing analysis flows Experience in calibration to hardware/measurements...

Location: Santa Clara, CA
Posted Date: 22 Oct 2025

Design Verification Lead

your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team..., and tests using System Verilog and UVM Debug RTL simulations and work with HW and FW development teams to verify fixes Review...

Posted Date: 09 Oct 2025