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Keywords: RTL Lead, Location: Bangalore, Karnataka

Page: 11

Associate III - VLSI DFT CAD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Associate III - VLSI STA

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Associate III - VLSI DFT_N

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Senior Principal Engineer, Physical Design

design capabilities and infrastructure in alignment with company-wide technology strategy. Lead RTL-to-GDSII implementation..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...

Company: Marvell
Posted Date: 13 Dec 2025

Senior Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration...

Company: Marvell
Posted Date: 13 Dec 2025

Senior Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing...

Company: Marvell
Posted Date: 13 Dec 2025

Staff Synthesis & STA Engineer

About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs... with large digital & analog interfaces. You'll influence implementation, guide methodology improvements, and lead small...

Posted Date: 12 Dec 2025

Staff DV Engineer

and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal... Strategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key...

Posted Date: 12 Dec 2025

Staff Engineer, STA

Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs..., Tempus). Implement ECOs for timing fixes and validate changes. Collaborate with RTL, physical design, and DFT teams...

Posted Date: 06 Dec 2025

NPU / AI Processor Synthesis Engineer

to ensure high-quality netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate... General Summary: Job Description Role Overview The NPU Synthesis Lead will be responsible for driving synthesis...

Company: Qualcomm
Posted Date: 06 Dec 2025

Staff Engineer, Design Verification Engineering

Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing... Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor...

Posted Date: 06 Dec 2025

Senior ASIC Engineer, Switch SoC

is a plus. Background in RTL Build and Design Automation is a plus. Ways to stand out from the crowd: Chip lead type of technical... in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical...

Company: Nvidia
Posted Date: 05 Dec 2025

Staff Engineer, DFT Engineering

scan structures Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance..., ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . We are seeking a SoC DFT Lead...

Posted Date: 04 Dec 2025

FPGA Design Verification Engineer

Job Description: UST Job Title: Technical Lead II - VLSI Who we are: At UST, we help the world... verification methodologies (e.g., UVM, System Verilog, RTL). Write and debug test cases to verify functionality, performance...

Company: UST
Posted Date: 27 Nov 2025

Program Manager - Pre-Silicon Platform Emulation

enablement. Lead triage and resolution of blocking issues in coordination with architecture, validation, and debug teams... management experience and an overall industry experience of 15+ years Good understanding of SoC architecture, RTL integration...

Posted Date: 27 Nov 2025

PNR PD STA Senior staff

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service..., or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence...

Posted Date: 23 Nov 2025

Serdes PHY Analog Design Engineer

sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.... Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC...

Company: Qualcomm
Posted Date: 22 Nov 2025