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Keywords: RTL Lead, Location: Bangalore, Karnataka

Page: 2

Senior Principal Engineer, RTL ASIC Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact About Marvell Marvell... is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions Business Unit closely...

Company: Marvell
Posted Date: 09 Jan 2026

Senior Staff Engineer - RTL ASIC Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff... block, microarchitecture of one or more blocks. Implement a specification using RTL coding techniques and best practices...

Company: Marvell
Posted Date: 07 Jan 2026

Staff Engineer, RTL Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Staff Engineer..., microarchitecture of one or more blocks. Implement a specification using RTL coding techniques and best practices Work with the...

Company: Marvell
Posted Date: 07 Jan 2026

Principal Engineer, RTL ASIC Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit... with cross-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices...

Company: Marvell
Posted Date: 07 Jan 2026

Infra NOC (RTL)Design Engineer-Staff/Sr Staff

General Summary: NoC design lead and is part of BDC infrastructure (NoC/Interconnect) core team Responsible... Solving Lead by example on customer problem solving related to NoC/Interconnect Minimum Qualifications: 8+ years...

Company: Qualcomm
Posted Date: 04 Jan 2026

NoC (RTL) Design - PE/Director

design lead and is part of BDC infrastructure (NoC/Interconnect) core team Responsible for specification, design... an impact on product competitiveness, roadmap and business objectives through Design/DV/Problem Solving Lead by example...

Company: Qualcomm
Posted Date: 25 Nov 2025

Senior Technical Manager-RTL

in RTL design and development, as well as proven leadership abilities. Responsibilities: - Lead and manage a team...Job Requirements Job Title: Senior Technical Manager-RTL Job Type: Full-Time We are seeking a highly skilled...

Company: Quest Global
Posted Date: 19 Nov 2025

RTL / IP Design Engineer

your career. Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC for integration as well...

Posted Date: 10 Dec 2025

DFT (RTL) Engineer

. Lead Cross-Site Collaboration Coordinate with teams across multiple locations to ensure cohesive and unified DFT...

Posted Date: 22 Nov 2025

Physical Design Low Power Lead

your career. MTS/SMTS SILICON DESIGN ENGINEER THE ROLE: As a low power lead in AMD India cores team, you will work to verify... and optimization. Oversee and manage power convergence and sign-off procedures across various SOC classes. Conduct RTL power analysis...

Posted Date: 14 Jan 2026

Lead Product Engineer

. Job Title: Lead Product Engineer Location: Bangalore About Us Cadence is a pivotal leader in electronic design, building... Overview Join a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP...

Posted Date: 14 Jan 2026

Core Logic Design Lead

Architecture for CPU on-chip/off-chip network, MP coherency and last level system caches. Strong RTL design expertise and hands... submission of your application. Job Title Core Logic Design Lead Job ID 85458 City / Township / Village BANGALORE...

Company: IBM
Posted Date: 11 Jan 2026

Logic Design Lead - Power Management

. Your role and responsibilities As Logic Lead for Power Management, you will be responsible for design and development... of power management and sustainability features for high performance Processors chips. Lead the Development of features...

Company: IBM
Posted Date: 11 Jan 2026

GFX- IP Verification Lead

will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank... EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools...

Posted Date: 10 Jan 2026

IP/Subsystems Design Verification Lead

, you will help bring to life cutting-edge designs. You will lead a front-end design verification team, and work closely... will have experience leading a team verifying RTL for IP or subsystems and understand architectural specifications. Responsibilities...

Posted Date: 10 Jan 2026

Physical Design Lead

, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . Role Overview The Lead... with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints...

Posted Date: 09 Jan 2026

Lead GPU Verification Engineer

, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features.... Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test...

Posted Date: 30 Dec 2025

Lead FW/SW Validation

Job Description: Lead FW/SW Validation Position Overview We are seeking a motivated Firmware Developer... with hardware engineers to define and implement hardware-software interfaces. Deployment of RTL files on pre silicon platforms...

Posted Date: 30 Dec 2025

Technical Lead - FPGA

growth of the local aviation industry. Key Responsibilities and Tasks As a Senior Technical Lead FPGA Design... and validation Microarchitecture and digital logic circuit development RTL development using VHDL, test through developer test...

Company: Thales
Posted Date: 21 Dec 2025

DV Lead Engineer

Job Requirements Job Summary: We are looking for a highly skilled and hands on Lead Engineer to lead and drive... & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution. Define...

Company: Quest Global
Posted Date: 20 Dec 2025