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Keywords: SOC Validation Engineer, Location: San Jose, CA

Page: 1

SOC Validation Engineer

your career. THE ROLE: We are looking for a dynamic, energetic SOC Validation Engineer to join our growing Systems Validation... in ensuring the quality of AMD's next-generation FPGA and SoC products. As an experienced validation engineer, you'll work...

Posted Date: 09 Jan 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture... specification through production silicon, working on complex IP design. THE PERSON: The ideal candidate is a seasoned ASIC/SOC...

Posted Date: 21 Feb 2026

Physical Design Engineer (ASIC / SoC) in San Jose, CA

Join a leading custom ASIC and System-on-Chip (SoC) development company delivering high-performance silicon solutions... across emerging technologies. As a hands-on Physical Design Engineer, you’ll own projects from feasibility through tape-out...

Posted Date: 12 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

your career. ASIC DESIGN ENGINEER THE ROLE: Join AMD's Silicon Design team to design and develop cutting-edge IPs... for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro...

Posted Date: 08 Feb 2026

ASIC/SoC Design Engineer

of Adaptive SoC and FPGA configuration system. THE PERSON: You are passionate about complex Adaptive SoC and FPGA..., verification, physical design integration, and post-silicon validation. Integrate complex configuration blocks into full-chip...

Posted Date: 21 Feb 2026

Senior FPGA Validation Engineer

knowledge about SOC architecture, and emulation and prototyping platforms. As the Senior FPGA Validation Engineer for Axiado... Validation Engineer position is your opportunity to join one of the industry’s leading companies in platform security management...

Company: Axiado
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $80000 - 200000 per year

Electrical Design Validation Engineer

Electrical design validation engineer for validating the power and high speed interfaces in hardware prototypes consists of SOC..."Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential TMR ID: M1TQJA Role: Electrical Design Validation...

Posted Date: 13 Feb 2026

Power & Thermal Validation Engineer III

Job Description: Power & Thermal Validation Engineer III Lead II - Semiconductor Product Validation Who... lives of people across the world. Visit us at UST.com. You Are: We are seeking a highly experienced engineer...

Company: UST
Location: San Jose, CA
Posted Date: 05 Feb 2026

DFT (Design For Test) Engineer

Design For Testability (DFT) Engineer to join our dynamic team. The ideal candidate will be responsible for ensuring the... responsibilities Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage...

Company: Etched
Location: San Jose, CA
Posted Date: 01 Mar 2026
Salary: $15000 - 27000 per year

Lab HW Engineer

supporting ASIC or SoC bring-up and validation. Prior experience with sockets, pogo pins, packages, and mechanical constraints.... Our engineers handle every aspect of chip development, from definition and architecture to silicon bring-up, validation, and system...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 27 Feb 2026

RF / HW Test Engineer

Engineer with our client located in San Jose, CA. Job Description: GNSS SoC location group is seeking a RF/HW Test engineer...Job Title: RF/HW Test Engineer Position Description: Protingent Staffing has an exciting contract RF / HW Test...

Company: Protingent
Location: San Jose, CA
Posted Date: 24 Feb 2026
Salary: $55 - 65 per hour

Senior 5G/LTE Protocol & Certification Engineer

enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 20 Feb 2026

Senior 5G/LTE Protocol & Certification Engineer

to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 18 Feb 2026

Senior Technical Staff Engineer - Design for Test

/External/job/Senior-Technical-Staff-Engineer---Architect--DFT-Lead-_R430-26-1 The DFT lead works in close partnership..., and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved...

Company: Microchip
Location: San Jose, CA
Posted Date: 11 Feb 2026

ASIC Engineer

. Your Impact As an ASIC Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll... cause simulation, software bring-up, and customer failures Perform diagnostic and post silicon validation tests in the lab...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026
Salary: $135800 - 193400 per year

IP Design Engineer

your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive..., you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package...

Posted Date: 16 Jan 2026

Product Development Engineer

* Define and execute characterization and silicon validation plans for high-speed transceivers Define methodologies... for characterization and silicon validation of high speed serial systems Characterize high speed SERDES 100Gbps with automated flows...

Posted Date: 27 Feb 2026

ASIC Design Verification Engineer

of complex issues during bring-up and post-silicon validation. Minimum Qualifications Bachelors + 7 years of related... and large-scale SoC architectures. Experience with advanced emulation, prototyping, and formal verification tools at scale...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Feb 2026

ASIC Design Verification Emulation Engineer

and post-silicon validation. Minimum Qualifications Bachelors + 7 years of related experience, or Masters + 4 years... or best practices in ASIC verification. Deep expertise in multiple protocols and large-scale SoC architectures. Experience...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Feb 2026

ASIC Engineer

of complex issues during bring-up and post-silicon validation Minimum Qualifications Bachelors + 7 years of related... standards or best practices in ASIC verification. Deep expertise in multiple protocols and large-scale SoC architectures...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026