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Keywords: SOC Verification Lead, Location: Bangalore, Karnataka

Page: 5

RTL Design Lead - CPU Team

design as well as verification/design quality. You are a team player who has excellent communication skills... crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC...

Posted Date: 17 Dec 2025

Lead MTS Physical Design

an exceptional Lead Physical Design Engineer to join our MIC team in Bangalore. In this role, you will be working with some of the... ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take complete ownership...

Company: Rambus
Posted Date: 13 Dec 2025

Digital Front-End Lead

and systems across numerous sectors. About The Job: We are looking for a highly skilled Digital Front-End Lead to drive... and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The...

Company: Varite
Posted Date: 07 Dec 2025

Technical Lead I - VLSI

Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis... / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow...

Company: UST
Posted Date: 04 Dec 2025

LEAD PLATFORM EMULATION ENGINEER

your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification... with BIOS/OS bring up on full X86 SOC emulation platform Proficient in IP level ASIC verification, experience working with CPU...

Posted Date: 26 Nov 2025

Lead Software Engineer (Safety/MCAL)

FPGA Prototype/Emulation Lead – Platform Software & FPGA Team Location: Pune / Bangalore – India Join the RISC...: We are seeking highly skilled FPGA and emulation engineer/lead to join our team and help us build FPGA designs for our CPU’s (64-bit...

Posted Date: 23 Nov 2025

Senior RTL Design Lead

or significant interest in fabric design for complex SOC . You have had significant success driving architecture, product roadmaps.... This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding...

Posted Date: 20 Nov 2025

RTL/IP Design Lead

architecture, Verification and Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate... SoC requirements on power, performance, Area targets Digital design implementation and micro-architecture...

Posted Date: 20 Nov 2025

Senior Lead RTL Design Engineer

your career. LEAD ENGINEER - RTL DESIGN THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life... SoC requirements on power, performance, Area targets Digital design implementation and micro-architecture...

Posted Date: 19 Nov 2025

Technical Lead II - VLSI

/B.E/M.Tech/M.E Skills: vlsi design,design verification,soc design,systemverilog, About Company: UST is a global...Job Description: Job Description: Title: Design Verification Engineers req for full chip verification Role...

Company: UST
Posted Date: 11 Feb 2026

AI/ML driven ASIC Design and Implementation Lead Automation Engineer

design, SoC Design, Verification, Implementation and Design Enablement teams to drive new ways of working, improvements... to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and verification...

Posted Date: 30 Jan 2026

IP/ Subsystem - RTL Design Lead

), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification... with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD and other 3rd party IPs...

Posted Date: 24 Jan 2026

DDRPHY Senior Staff/Staff/ Lead Digital Design Engineer

for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan... for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience...

Company: Qualcomm
Posted Date: 07 Jan 2026

Technical Lead I - VLSI

Job Description: SoC level verification using UVM, Verilog, SystemVerilog, C/C++. * Develop UVM-based frameworks... will be added advantage. * NoC based verification, can be Sub-system/SoC level verification. Skills: firmware,uvm,verilog...

Company: UST
Posted Date: 04 Jan 2026

Lead RTL Design Engineer

, and Interface with verification/validation teams to ensure design quality and robustness. Build strong collaboration with other R...&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones. Promote...

Posted Date: 30 Dec 2025

Technical Lead I - VLSI

Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis... / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow...

Company: UST
Posted Date: 04 Dec 2025

MBIST CAD/Methodology Development Engineer, Senior Lead

semiconductor process nodes. In this role, you will be part of a global technical team collaborating across SoC Design, DFT, Product... in MBIST domain Skills Required Deep expertise in MBIST, including planning, insertion, verification, vector generation...

Company: Qualcomm
Posted Date: 04 Dec 2025

Silicon - Performance Analysis Lead/Staff Engineer

Summary: Job Overview The candidate will be part of the SOC Infrastructure IP Performance modelling and analysis team..., Should have understanding of Computer architecture, mobile SOC ARCH. Experience with industry standard automation and scripting (C/C++/Shell...

Company: Qualcomm
Posted Date: 29 Nov 2025

DFT Mid Senior Engineer

silicon. Key Responsibilities DFT Architecture & Implementation Lead Execute DFT activities for complex ASIC/SoC designs...Job Title DFT Mid Level Engineer (ASIC / SoC) Experience 6-8 Years Location Bengaluru Employment Type Full-time...

Company: Best NanoTech
Posted Date: 16 Feb 2026

Physical Design ( PD) Mid Senior Engineer

closure, sign-off quality, and optimal PPA for ASIC/SoC designs. Key Responsibilities Lead and execute physical design... implementation. The candidate will lead and execute end-to-end physical design activities from RTL to GDSII, ensuring robust timing...

Company: Best NanoTech
Posted Date: 16 Feb 2026