. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively... architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The...
include IP and subsystem design verification and working collaboratively with the IP/SoC team. Key Responsibilities..., you will help bring to life cutting-edge designs. You will lead a front-end design verification team, and work closely...
include IP and subsystem design verification and working collaboratively with the IP/SoC team. Key Responsibilities..., you will help bring to life cutting-edge designs. You will lead a front-end design verification team, and work closely...
crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC... of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL...
's Bangalore office, this role offers a position in Digital Design working on IP subsystem and cores targeted to a variety... of industry leading RFIC chips. Responsibilities include: Develop micro-architecture and RTL design for cores related to RFIC...
in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design. Experience in testbench... design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor...
Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact About Marvell Marvell...
with cross-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit...
them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP... level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads...
Lead End to End IP/Subsystem/SOC Verification Develop Verification Strategy for any given Design. Architect, Develop... of experience in IP/Subsystem/SoC verification & post silicon debug Excellent design and verification concepts Experience in ARM...
Job Description Be part of the DDR PHY IP Front End Design team responsible for - Develop firmware for DDR5 PHY... on Microcontrollers. Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms...
automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow... RESPONSIBILITIES: The successful candidate will own/lead the DFX Design architecture and implement cutting edge DFX features...
of innovation. As a Fellow-level Verification Architect, you will define and lead the verification architecture and methodology... for next-generation high-speed interface PHY IP designs (DDR, LPDDR, USB, PCIe, and emerging standards). You will set the strategic...
and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY... a team to develop RTL for SoC subsystems and understand architectural specifications. Responsibilities include IP...
Engineer – Memory IP Products Join a growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY... Verilog RTL design and gate level verification experience Synthesis and static timing analysis experience (physical...
. Position Requirements Experience working with UCIe, PCIe, Ethernet, 112G or similar interface IP. Verilog RTL design.... Job Title: Lead Product Engineer Location: Bangalore About Us Cadence is a pivotal leader in electronic design, building...
Subsystem/SOC Design Verification for an ARM based SoC Design. Extensive experience in SV/UVM based SOC or IP Verification... & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution. Define...
cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues Responsible..., GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools Good understanding...
Deep expertise in Testbench Architecture using SystemVerilog and UVM at IP, ASIC, and/or SoC level. Strong knowledge... of layered UVM environments, reusable testbench components, and block/subsystem/SoC-level verification strategies. Solid...
on Synthesis/STA of 4+ successful tapeouts at lower geometries Familiar with digital flow design aspects RTL to GDS Proficiency... About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs...