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Keywords: IP/Subsystem Verification Lead, Location: Bangalore, Karnataka

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IP/Subsystem Verification Lead

include IP and subsystem design verification and working collaboratively with the IP/SoC team. Key Responsibilities..., you will help bring to life cutting-edge designs. You will lead a front-end design verification team, and work closely...

Posted Date: 07 Nov 2025

IP Verification Lead(Leadership Role)

, environments, and coverage strategies for complex IP blocks. Subsystem Verification: Ensure seamless integration and verification.... Deep expertise in IP and subsystem-level verification, including UVM/SystemVerilog, formal verification, and emulation...

Posted Date: 08 Nov 2025

IP Design Verification Engineer

Job Details: Job Description: As the Turbo IP (TIP) Verification technical Lead, you will own and drive the... experience and minimum 10+ years of experience in ASIC/IP verification Deep expertise in IP and subsystem-level verification...

Company: Intel
Posted Date: 19 Dec 2025

Wireless R&D IP Verification Engineer, Principal

Leadership Define and own verification strategy for IP/Block/Subsystem-level DV. Guide the team in developing robust.... Required Skills & Experience Vast experience in IP-level design verification Strong expertise in SystemVerilog/UVM and coverage...

Company: Qualcomm
Posted Date: 11 Dec 2025

Lead Design Verification Engineer

and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics Lead IP... background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification Proven deep expertise...

Company: Intel
Posted Date: 28 Dec 2025

Senior Lead Verification Engineer

in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop... with the Security IP Team (SECIP). The primary focus of this role is to Lead the team responsible for Hardware/Firmware...

Posted Date: 24 Dec 2025

SOC Design Verification - Lead/Senior Architect

across fabric. Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools & methodology... your career. SMTS SILICON DESIGN ENGINEER THE ROLE (SOC Verification Lead): Drive and lead the SOC level verification...

Posted Date: 12 Dec 2025

Design Verification Lead

Lead End to End IP/Subsystem/SOC Verification Develop Verification Strategy for any given Design. Architect, Develop... of experience in IP/Subsystem/SoC verification & post silicon debug Excellent design and verification concepts Experience in ARM...

Company: Quest Global
Posted Date: 22 Nov 2025

RTL Design Lead - IP Design

. You will lead a front-end design and integration team, working closely with the architecture, IP design, Physical Design teams... and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY...

Posted Date: 18 Dec 2025

Director, Chassis Design Verification

comprehensive verification methodologies, lead technical development, and deliver first-pass silicon success through best-in-class... IP design and verification practices. This role requires deep technical expertise across advanced DV methodologies...

Company: Intel
Posted Date: 28 Dec 2025

Principal Engineer, Design Verification

of experience in IP/Subsystem/SoC Verification Expertise in design verification methodologies using SystemVerilog UVM and/or formal... verification techniques Experience in defining Testbench Architecture for complex IP’s, Subsystems and SoC’s Strong knowledge...

Posted Date: 12 Dec 2025

SOC Verification Engineer: Security DV

, Booting, Algorithms SHA,AES,RSA) and subsystem or signature IP’s in the complex SOC. He will be responsible for verifying.... To take complete IP integration responsibility, including the deployment verification. Understand spec, interact with customer, team...

Posted Date: 10 Dec 2025

SOC level verification - PCIE, USB, Ethernet

verification activities for GDP (PCIE,USB,Ethernet,I2C,I3C,Uart,SPI) and subsystem or signature IP’s in the complex SOC. He... (I2C,I3C,UART,SPI) Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools...

Posted Date: 28 Nov 2025

Design Verification Senior Principal Engineer

improvements in DV processes for efficient and high-quality execution · Collaborate with IP, Subsystem, and SoC teams on test plan... creation, testbench architecture, and milestone reviews · Work closely with Design and DV teams across IP, Subsystem, and SoC...

Company: Marvell
Posted Date: 16 Nov 2025

Design Verification Senior Principal Engineer

. Define and drive improvements in DV processes for efficient and high-quality execution . Collaborate with IP, Subsystem... across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations...

Company: Marvell
Posted Date: 12 Nov 2025

Sr. Manager Design Verification

, environments, and coverage strategies for complex IP blocks. Subsystem Verification: Ensure seamless integration and verification.... Deep expertise in IP and subsystem-level verification, including UVM/SystemVerilog, formal verification, and emulation...

Posted Date: 29 Oct 2025

DV Lead Engineer

Subsystem/SOC Design Verification for an ARM based SoC Design. Extensive experience in SV/UVM based SOC or IP Verification.... Key Responsibilities: Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development...

Company: Quest Global
Posted Date: 20 Dec 2025

Sr RTL Design Lead

crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC... design as well as verification/design quality. You are a team player who has excellent communication skills...

Posted Date: 17 Dec 2025

LEAD PLATFORM EMULATION ENGINEER

your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification... with BIOS/OS bring up on full X86 SOC emulation platform Proficient in IP level ASIC verification, experience working with CPU...

Posted Date: 26 Nov 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 25 Oct 2025