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Keywords: IP/Subsystem Verification Lead, Location: Bangalore, Karnataka

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IP/Subsystem Verification Lead

junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected..._ THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification...

Posted Date: 27 Feb 2025

RTL/Integration- Subsystem/IP Design Lead

of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery... to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification...

Posted Date: 23 Apr 2025

DSP IP SS Design Verification - Sr Lead Engineer

Job Responsibilities: Drive design verification of DSP Subsystem IP by working with a global DSP design team involving architecture... at IP level and insure high quality commercial success of our products Assertions, simulation, formal verification (static...

Company: Qualcomm
Posted Date: 28 Mar 2025

Verification Engineer, Digital IP

on IP/Sub-System Verification Proven experience in testbench design and development using UVM methodology for IP/Subsystem...Job Title: Sr. Lead Verification Engineer Primary Location: Bengaluru, India Role Summary: We are part of MCU/MPU...

Posted Date: 14 Feb 2025

Sr. Principal Verification Engineer, Digital IP

on IP/Sub-System Verification Prior experience as a tech lead or DV manager is strongly preferred Proven experience... safety and security standards. Job Responsibility: Responsible for the pre-silicon verification of IP modules or, IP...

Posted Date: 08 Feb 2025

DSP Design Verification Sr Lead Engineer

and royalties from intellectual property. Job Responsibilities: · Drive design verification of DSP IP by working with a global..., and meet coverage goals. · Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails...

Company: Qualcomm
Posted Date: 07 May 2025

Sr Lead Design Verification

. Job Description: Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR... successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications...

Company: Qualcomm
Posted Date: 22 Mar 2025

DSP / NPU Design Verification Sr Lead Engineer

and royalties from intellectual property. Job Responsibilities: · Drive design verification of DSP IP by working with a global..., and meet coverage goals. · Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails...

Company: Qualcomm
Posted Date: 07 Mar 2025

DSP / NPU Design Verification Sr lead Engineer

from chipsets and royalties from intellectual property. Job Responsibilities: · Drive design verification of DSP IP by working... environments, and meet coverage goals. · Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level...

Company: Qualcomm
Posted Date: 28 Feb 2025

Staff / Principal GPU Verification Engineer

demands and improvements for graphics IP. You will: Oversee all verification activities for a GPU component or subsystem... verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification...

Posted Date: 28 Feb 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 21 Mar 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 21 Mar 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 15 Mar 2025

Firmware Lead- Memory (DDR/LPDDR)

root-cause complex failure mechanisms at the IP, subsystem and/or system level. Prior experience and/or exposure... PREFERRED EXPERIENCE: Good understanding of firmware development cycle, integration and verification/validation for pre...

Posted Date: 26 Apr 2025

Firmware Lead- Memory (DDR/LPDDR)

IP, subsystem and/or system level. Prior experience and/or exposure to testing platforms (Simulation and/or Emulation... of firmware development cycle, integration and verification/validation for pre-si and post-si for SoC designs. Expertise in low...

Posted Date: 24 Apr 2025

Digtal Bench Characterization Engineer, Sr Lead

Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOC..., you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components...

Company: Qualcomm
Posted Date: 23 Apr 2025

Post Si Validation Sr Lead Engineer

considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional... validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre...

Company: Qualcomm
Posted Date: 15 Mar 2025

Principal Design Engineer

experiments to root cause PHY/Link Level issues and lead debug/resolution efforts in collaboration with Design/Verification teams... its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts...

Posted Date: 12 Apr 2025

Senior Director Engineering

productization. You’ll provide leadership in the development of highest value-add IP, subsystem & SoC plans and strategies.../Networking domain. Expert in developing IP, subsystem, Chiplets and SOCs Experience with one or more high-speed IO technologies...

Company: Marvell
Posted Date: 26 Mar 2025

Principal Engineer, RTL ASIC Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions...-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices Work...

Company: Marvell
Posted Date: 23 Mar 2025