Job Title: STA/SDC Engineer Duration: 12+ Months Location: San Jose, CA Technical: Being a member of design team... who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing...
Position: SDC Engineer (eInfochips Inc) Job Description: Position: SDC Engineer (eInfochips Inc) Location: San..., and to bring fullchip SDC changes back to block level. Helping develop and apply methodology to ensure correctness and quality...
Position: STA Engineer (eInfochips Inc) Job Description: Position: STA Engineer (eInfochips Inc) Location: San..., and to bring fullchip SDC changes back to block level. Helping develop and apply methodology to ensure correctness and quality...
_ THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring... timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL...
on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies. · Work on SDC constraints, advanced OCV.../SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. · Work efficiently with R&D and customer...
/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups..., exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel...
Technical: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams... integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes...