Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Senior ASIC Physical Design and Timing Engineer, Location: Santa Clara, CA

Page: 1

Senior ASIC Physical Design and Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic... in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis. Expertise in physical design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

Senior ASIC Timing Engineer

. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual..., and timing convergence. In-depth understanding of multiplexed scan logic and constraints. Expertise in physical design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Jun 2025

Senior Staff Physical Design Engineer - Static Timing Analysis

a Senior Staff Physical Design Engineer – Static Timing Analysis (STA) to join our growing team. In this role...: RTL, synthesis, physical implementation, and signoff Debug and resolve complex timing violations and drive design fixes...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 31 May 2025
Salary: $124420 - 186400 per year

Senior Timing and Constraints Methodology Engineer

, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology... engineer to develop pioneering timing sign-off strategies for next-generation GPUs and SoCs. In this role, you’ll develop...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 May 2025

Senior ASIC Floorplan Design Engineer

We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer..., interconnect and floorplan improvement opportunities Solve timing and routing congestion issues with physical and ASIC design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 May 2025

Senior ASIC Design Engineer

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU... with verification engineers. Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 02 May 2025

Sr Principal ASIC Design Engineer (NetSec)

team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer.... You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit...

Location: Santa Clara, CA
Posted Date: 08 Jun 2025

Sr Principal ASIC Design Engineer (NetSec)

team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer.... You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit...

Location: Santa Clara, CA
Posted Date: 07 Jun 2025

Senior ASIC Synthesis Engineer

. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem solver and highly motivated... with physical design to address timing, area, congestion tradeoffs Drive timing closure and power/area optimization...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

Senior Reset and Boot ASIC Engineer

NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 18 Jun 2025

Senior Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Physical Design.... Experience with chiplet-based architectures and full-chip physical design a plus. Experience in static timing analysis (STA...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 24 Jun 2025
Salary: $124420 - 186400 per year

Senior Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Physical Design... architectures and full-chip physical design a plus. Strong experience in static timing analysis (STA), with a focus on timing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Jun 2025
Salary: $124420 - 186400 per year

Principal Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance... of developing and implementing intricate timing and logic ECOs. Collaboration is key, and you will work closely with the RTL design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 18 Jun 2025
Salary: $146850 - 220000 per year

Senior Principal Digital IC Design Engineer

microprocessors. RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block...-level functional verification. Experience in implementation/timing closure for high speed design. Hands-on experience...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Jun 2025