. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly... clearance. Roles and Responsibilities: Responsible for static timing analysis on digital designs to ensure timing...
would be a plus Active Clearance or higher Senior Principal Engineer Basic Qualifications: Bachelor’s degree with 8 years of experience... as required to accomplish the goals. Principal Engineer Basic Qualifications: Bachelor’s degree with 5 years of experience, a Master...
Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools Developing...), SDC (Synopsys Design Constraints) Basic Qualifications for Sr. Principal Digital ASIC Circuit Design Engineer Level...
and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...
and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...
using industry-standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static... delivery of clean GDSII for tapeout, with full verification signoff. Perform full-chip and block-level static timing analysis...
, synthesis, static timing analysis, LEC, CDC/RDC, and power analysis. Tools & Methodologies: -- Proficiency with EDA tools.... As a High-Speed DSP Design Engineer, you will play a key role in micro-architecting and developing next-generation DSP...
advanced physical design methodologies and flows Strong knowledge on static timing analysis (PrimeTime, Tempus), EM/IR-Drop... and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data...
advanced physical design methodologies and flows Strong knowledge on static timing analysis (PrimeTime, Tempus), EM/IR-Drop... and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data...
, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification..., place and route, and timing signoff. Collaborate with the verification team on pre-silicon verification tasks...