to minimize ECO cycles and accelerate signoff readiness. Requirements: 8+ years’ hands-on experience in ASIC synthesis...Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint...
to minimize ECO cycles and accelerate signoff readiness. Requirements: 8+ years' hands-on experience in ASIC synthesis...Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint...
Grow with us Our Exciting Opportunity: This is an on-site, hybrid opportunity. This is not a remote work opportunity... to make sure that the final ASIC achieves the goals of the program. What you will do: Be an empowered designer tasked...