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Keywords: Sr. Principal Verification Engineer, Location: San Jose, CA

Page: 1

Sr. Principal Verification Engineer

an exceptional SPE Verification Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working... chip and functional blocks. Develop/maintain verification environments for chip level verification and enhance/use the...

Company: Rambus
Location: San Jose, CA
Posted Date: 12 Feb 2026

Sr. Principal Software Engineer, Synthesis

. Job Description Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence... synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing...

Posted Date: 28 Jan 2026

Sr Principal Product Engineer – Memory IP

an impact in our world. We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug... / Optional Skills Exposure to STA and RTL flows would be beneficial. Familiarity with advanced mixed-signal verification...

Posted Date: 23 Nov 2025