Find your dream job NOW!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Synopsys, Location: Bangalore, Karnataka

Page: 9

Associate III - VLSI STA

Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS... with RTL designers for constraint development and cleanup. • Proficient in Synopsys/Cadence tools with hands-on experience...

Company: UST
Posted Date: 17 Dec 2025

DV CPU_ARM

on simulators (e.g., Cadence Xcelium, Synopsys VCS, Mentor QuestaSim). Debug complex functional and performance issues, identifying...

Company: Quest Global
Posted Date: 16 Dec 2025

DV SV UVM_DRAM

, DDR, Ethernet, or similar. Tools: Proficiency with industry-standard EDA simulation tools like Synopsys VCS, Cadence... simulation tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa. Scripting: Strong scripting skills in a language...

Company: Quest Global
Posted Date: 16 Dec 2025

Senior Physical Design Engineer

and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing...

Company: Nvidia
Posted Date: 16 Dec 2025

Senior Engineer, Physical Design

with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler...

Company: Marvell
Posted Date: 13 Dec 2025

CAD ENGINEER

in using Synopsys Fusion Compiler and other EDA tools and internally developed scripts. L1-LK1 Responsibilities: MS... tools is a must (Synopsys Fusion Compiler). Preferably on multi-million gate designs in mature node technologies (65nm...

Company: onsemi
Posted Date: 12 Dec 2025

Staff DV Engineer

(Cadence/Synopsys) and formal verification techniques Scripting and Automation: Advanced proficiency in Python, Perl, TCL...

Posted Date: 12 Dec 2025

Network-on-chip/interconnect Design -Staff Engineer

, coherency protocols and virtualization. Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT...

Company: Qualcomm
Posted Date: 11 Dec 2025

DSP / NPU Senior Staff Design Verification Engineer

annotated and power aware. · Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence...

Company: Qualcomm
Posted Date: 11 Dec 2025

Senior Lead Design Verification Engineer

, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog...

Company: Qualcomm
Posted Date: 11 Dec 2025

NPU / AI Processor Synthesis Engineer

-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop...

Company: Qualcomm
Posted Date: 06 Dec 2025

MBIST Diagnostics Engineer - Sr Staff/Staff Engineer

., Mentor Tessent, Synopsys etc). Strong analytical and problem-solving skills with a data-driven mindset. Excellent...

Company: Qualcomm
Posted Date: 06 Dec 2025

Staff Engineer, Design Verification Engineering

: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques Scripting...

Posted Date: 05 Dec 2025

DFT Lead - Design for Test - ATPG

, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool...

Posted Date: 05 Dec 2025

SOC DFT & Test Manager

environments, including diagnostic log analysis and tester pattern debug. Proficiency with major EDA tools (Synopsys, Cadence...

Posted Date: 05 Dec 2025

Technical Lead I - VLSI

: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus...

Company: UST
Posted Date: 04 Dec 2025

MBIST CAD/Methodology Development Engineer, Senior Lead

, memory repair, and diagnostics. Strong hands-on experience with MBIST EDA tools (e.g., Synopsys SMS, Tessent MBIST...

Company: Qualcomm
Posted Date: 04 Dec 2025

Technical Lead I - VLSI

: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus...

Company: UST
Posted Date: 04 Dec 2025

Formal Verification Lead

-on expertise with formal verification tools (Synopsys VC Formal, JasperGold, Questa Formal / or equivalents). Deep understanding...

Posted Date: 04 Dec 2025

FPGA Design Verification Engineer

-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps). Experience with high-speed I/O design and protocols...

Company: UST
Posted Date: 27 Nov 2025