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Keywords: System IP Design Verification Engineer, Location: San Jose, CA

Page: 2

STA/SDC Engineer

Job Title: STA/SDC Engineer Duration: 12+ Months Location: San Jose, CA Technical: Being a member of design team... modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient...

Posted Date: 25 Jun 2025

Contract Hardware Engineer Sr

our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate... with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC...

Posted Date: 14 Jun 2025

SDC Engineer (eInfochips Inc)

Position: SDC Engineer (eInfochips Inc) Job Description: Position: SDC Engineer (eInfochips Inc) Location: San... Jose CA (Day-1 Onsite) What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works...

Location: San Jose, CA
Posted Date: 07 Jun 2025

STA Engineer (eInfochips Inc)

Position: STA Engineer (eInfochips Inc) Job Description: Position: STA Engineer (eInfochips Inc) Location: San... Jose CA (Day-1 Onsite) What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works...

Location: San Jose, CA
Posted Date: 07 Jun 2025

Senior Staff Emulation Engineer - ZEBU

. The engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving synthesis and P&R... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 06 Jun 2025

Senior Staff Emulation Engineer - ZEBU

) and various solutions for emulation products. The engineer will also design and develop tests in VHDL/Verilog/System Verilog..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 04 Jun 2025

FPGA/ASIC Engineer

methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 15 Jun 2025

Contract Hardware Engineer Sr

-level IP integration. Collaborate with Software, Design, and Verification teams to validate the functional and performance... methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...

Company: LanceSoft
Location: San Jose, CA
Posted Date: 15 Jun 2025

FPGA/ASIC Engineer

methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 16 Apr 2025
Salary: $60 - 65.33 per hour