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Keywords: VLSI Design Optimization Engineer, Location: San Diego, CA

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VLSI Design Optimization Engineer

, while being aware of general VLSI CAD design principles. Implement tools using optimization tools like ILP, SAT, SMT, and various... to identify and solve VLSI design DTCO trade-offs, while being aware of general VLSI CAD design principles. This role will involve...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 29 Aug 2025
Salary: $115600 - 173400 per year

FE Design and Timing Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... timing optimization and implement the design for functionality. Generate and implement functional ECOs. Run static timing...

Company: Apple
Location: San Diego, CA
Posted Date: 25 Oct 2025

FE Design and Timing Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... timing optimization and implement the design for functionality. Generate and implement functional ECOs. Run static timing...

Company: Apple
Location: San Diego, CA
Posted Date: 25 Oct 2025

Cellular ASIC Methodology Engineer

! Description As a Cellular ASIC Methodology Engineer, you'll develop and optimize design and implementation methodology for integrated circuits... across multiple focus areas including area efficiency, power optimization, and design technology co-optimization. You'll design...

Company: Apple
Location: San Diego, CA
Posted Date: 14 Sep 2025

ASIC Methodology Engineer

technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools... DTECH Methodology team, you will work closely with core and SOC teams to enable a state-of-the-art design analytics platform...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 26 Nov 2025
Salary: $115600 - 173400 per year

Digital Test Engineer

, and optimization to maximize productivity. Assists in the assessment of complex design features to identify potential flaws... Summary: The Product Development and Test Engineering (PDTE) group is responsible for design validation, characterization...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 12 Nov 2025

EDA/CAD SW Engineer

- Netlist), Clock Tree Optimization, Exposure to VLSI design concepts, logic design * Excellent interpersonal and analytical... Summary: Qualcomm Technologies Inc's Global CAD team develops tools, flows, and methodologies for different aspects of VLSI...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 26 Oct 2025
Salary: $98500 - 147700 per year

EDA/CAD SW Engineer

and design patterns Experience in the areas of RTL Synthesis (System Verilog - Netlist), Clock Tree Optimization, Exposure... to VLSI design concepts, logic design * Excellent interpersonal and analytical skills with the ability to work independently...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 26 Oct 2025