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Keywords: Design Engineer, Location: Santa Clara, CA

Page: 5

ASIC Design Engineer - Cache Controller

, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency... of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

Applied Machine Learning Engineer, Circuit Design - New College Grad 2025

-silicon and Post Silicon custom circuit design and related data, Circuit/Layout Optimization and Spice correlation Work... on projects with applications ranging from analysis of silicon data, manufacturing process variation analysis, VLSI circuit design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $108000 - 184000 per year

ASIC Design Engineer - Cache Controller

, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency... of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

ASIC Design Engineer - Cache Controller

, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency... of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2025

Analog Design Engineer, Principal

design team providing high performance analog and mixed mode circuits for industry-leading Networking and Automotive Ethernet... products. Candidate will have opportunity to architect and design circuits for high performance transceivers and other critical...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 09 Oct 2025
Salary: $165630 - 248100 per year

Senior Principal Design Verification Engineer

, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design... that each design meets our customers’ specifications whether they’re a major hyperscaler company or telecom organization...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Oct 2025

Principal Design Verification Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As part of the Design Verification... that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Oct 2025
Salary: $146850 - 220000 per year

IP Design Engineer

of experience in digital design RTL coding experience using Verilog and/or System Verilog Strong in digital design, micro... speed interfaces IPs/Solutions Good understanding of system design aspects and its impact on performance and throughput...

Company: LanceSoft
Location: Santa Clara, CA
Posted Date: 04 Oct 2025

ASIC Design Engineer - New College Grad 2026

NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the... future of computing! What you'll be doing: As a key member of the GPU Design team, you will implement, document...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Oct 2025
Salary: $96000 - 161000 per year

IP Design Engineer

Design and develop Soft IP for FPGAs using Verilog/SystemVerilog Integrate third-party IP cores into FPGA systems...

Posted Date: 03 Oct 2025

Principal Engineer, Design Verification

-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Sep 2025
Salary: $146850 - 220000 per year

Senior Digital Design Engineer - High-Speed I/O and Photonics

, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Sep 2025

Principal Design Verification Engineer

-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low...-power techniques. As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $146850 - 220000 per year

Senior Staff Design Verification Engineer

-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $124420 - 186400 per year

Principal IC Design Engineer

As a member of our Santa Clara, CA/Champaign, IL-based design group, you will be responsible for transistor-level design..., design, and custom layout of high-frequency ICs used in advanced optical transceivers and other electro-optical systems...

Company: II-VI
Location: Santa Clara, CA
Posted Date: 26 Sep 2025

Physical Design Methodology Engineer, Innovus Flows - New College Grad 2025

’s work, to amplify human inventiveness and intelligence. What you will be doing: Developing innovative physical design... of the physical design flow on advanced technology nodes Develop flows for advanced place and route methods, floorplanning...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Sep 2025

Physical Design Engineer Intern - Master's Degree

the most difficult design problems in the areas of AI, data movement, memory/storage, switch, networking, security..., and other infrastructure applications. The Marvell Physical Design team is located in our Santa Clara, CA office, and has a long history...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Sep 2025
Salary: $27 - 55 per hour

Senior Layout Mask Design Engineer

, to amplify human creativity and intelligence. We are looking for you! You'll work on the design and development... of our next generation custom SRAM design. As part of the Digital IP Team, you will work with other team members on the new process design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $124000 - 195500 per year

Principal Silicon Design Engineer

and IP level design, SOC architecture and implementation strategies. THE PERSON: Excellent communication and presentation... design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology...

Posted Date: 20 Sep 2025

Senior Hardware Design Engineer, Ethernet Switching

. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet...-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 17 Sep 2025