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Keywords: Lead Applications Engineer – DDR Design IP, Location: San Jose, CA

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Lead Applications Engineer – DDR Design IP

to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving.... As a Lead Technical Presales Engineer, you will use your knowledge of different memory interface standards to architect memory...

Posted Date: 05 Oct 2025
Salary: $102900 - 191100 per year

Senior Applications Engineer – DDR Design IP

Applications EngineerDDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence...

Posted Date: 05 Oct 2025
Salary: $84000 - 156000 per year

Technical Staff Engineer - Architecture (System Interconnect)

Company Description https://wd5.myworkdaysite.com/en-US/recruiting/microchiphr/External/job/Technical-Staff-Engineer... at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth...

Company: Microchip
Location: San Jose, CA
Posted Date: 23 Sep 2025