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Keywords: Power Engineer (RTL Design & Verification), Location: Mountain View, CA

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Power Engineer (RTL Design & Verification)

Jobs Job Description Apply now Start Please wait... Job Title: Power Engineer (RTL Design & Verification) City: Mountain View State/Province... Contract Worker for RTL Design and Verification with expertise in power profiling and automation. The ideal candidate will play...

Company: Wipro
Location: Mountain View, CA
Posted Date: 13 Mar 2026
Salary: $80000 - 160000 per year

Principal Engineer, RTL Design - (Contract)

Role: Principal Engineer, RTL Design Location: Mountain View, CA (Onsite) Job Type: Contract Project... description The Principal Engineer, RTL Design within the NPU Hardware & Software organization, is a senior individual contributor...

Posted Date: 13 Mar 2026

Principal Engineer, RTL Design

Job Role: Principal Engineer, RTL Design Location: Mountain View, CA (Onsite) Duration: Long term contract Project... Description: The Principal Engineer, RTL Design within the NPU Hardware & Software organization, is a senior individual contributor...

Company: Stellent IT
Location: Mountain View, CA
Posted Date: 13 Mar 2026

FPGA Design Verification Engineer

Job Description: FPGA Design Verification Engineer Technical Lead II – VLSI Who We Are: Born digital, UST...: · Strong understanding of FPGA, ASIC, RTL design principles and architectures. · Proficiency in System Verilog and UVM verification...

Company: UST
Location: Mountain View, CA
Posted Date: 25 Jan 2026
Salary: $101000 - 152000 per year

Applications Engineering, Sr Staff Engineer- RTL-to-GDS/Fusion Compiler

Jobs Applications Engineering, Sr Staff Engineer- RTL-to-GDS/Fusion Compiler Sunnyvale, California, United States Engineering... design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 30 Jan 2026

Principal Physical Design Engineer

Principal Physical Design Engineer This role has been designed as ‘Hybrid’ with an expectation that you will work... with HPE. Job Description: Job Description: Physical Design Flow and P&R Development Engineer (Innovus / Fusion Compiler...

Posted Date: 10 Mar 2026

Principal VLSI Design Engineer, Sunnyvale, CA

, and power reports, and update RTL or micro‑architecture as needed. Participate in design reviews, provide clear feedback...Principal VLSI Design Engineer, Sunnyvale, CA This role has been designed as ‘’Onsite’ with an expectation...

Posted Date: 07 Mar 2026

Principal VLSI Design Engineer, Sunnyvale, CA

, and power reports, and update RTL or micro‑architecture as needed. Participate in design reviews, provide clear feedback...Principal VLSI Design Engineer, Sunnyvale, CA This role has been designed as ‘’Onsite’ with an expectation...

Posted Date: 28 Feb 2026

Principal Physical Design Engineer

Principal Physical Design Engineer This role has been designed as ‘Hybrid’ with an expectation that you will work... with HPE. Job Description: Job Description: Physical Design Flow and P&R Development Engineer (Innovus / Fusion Compiler...

Posted Date: 22 Feb 2026

Staff Digital Design Engineer

with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power... industry leaders. Lightmatter is (re)inventing the future of computing with light! We are hiring a Digital Design Engineer...

Company: Lightmatter
Location: Mountain View, CA
Posted Date: 18 Feb 2026

Physical Design Applications Engineer

optimization, and robust RTL-to-GDS flows using Synopsys tools. You Are You are an ASIC/physical design engineer with 2-4 years... Design Applications Engineer Sunnyvale, California, United States Engineering Employee $109000-$163000 Save...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 30 Jan 2026

Physical Design Lead (With STA & Timing Constraints Expertise)

on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability... machines. We lead in chip design, verification, and IP integration, empowering high-performance silicon chips and software...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 15 Feb 2026

ASIC Engineer Principal

& block-level Physical Design Engineer As a block-level and top-level SOC Physical Design Engineer, you will contribute... to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include: Responsibilities...

Posted Date: 13 Mar 2026

Principal Silicon Engineer

. Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification. Experience with the project...As a Principal Silicon Engineer, you will serve as the middle-engineering technical leader at the intersection of RTL...

Company: Microsoft
Location: Mountain View, CA
Posted Date: 01 Mar 2026

Senior FPGA Engineer, LEO Payload FPGA

. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions.... - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure...

Company: Amazon
Location: Sunnyvale, CA
Posted Date: 28 Feb 2026

Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist

design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial... engineering professional with a passion for solving complex challenges in silicon design and verification. You thrive in dynamic...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 28 Feb 2026

R&D Engineer, Sr Staff

used in chip design, verification and manufacturing. They work on assignments like designing, developing... of silicon design and verification technology. What You'll Be Doing: Designing and developing new features...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 26 Feb 2026

FPGA Architect / Senior FPGA Engineer (Altera & Xilinx)

failures Review RTL, constraints, and architecture for performance, power, and scalability Mentor junior engineers... understanding of: RTL design (Verilog/SystemVerilog; VHDL a plus) Clocking architectures, CDC, resets High-speed interfaces...

Company: InterSources
Location: Sunnyvale, CA
Posted Date: 20 Feb 2026

Technical Product Engineer

, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation... management team at Synopsys, focused on delivering state-of-the-art solutions for semiconductor design, verification...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 13 Feb 2026

Sr. Digital Mixed-Signal Architect

. You will also define the product and technological roadmaps along with suitable design and verification methodologies. You will report... against simulation prediction. Actively collaborate with the RTL and DV teams to enable block-level implementation and verification...

Posted Date: 08 Mar 2026