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Keywords: Senior RTL Analysis Methodology Engineer, Location: Santa Clara, CA

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Senior RTL Analysis Methodology Engineer

to do their best work. Come join the team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology... Engineer to join our Logic Design Implementation team. The team develops and supports static RTL verification methodologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Jan 2026

Senior Physical Design Methodology Engineer, Innovus Flows

engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA... at scale, in the shortest possible time. Your work in physical design methodology directly enables our speed to market...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... infrastructure is a plus. Proven hands-on experience with RTL-to-GDSII tool flows. physical design and analysis tools from EDA...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Power Methodology Engineer, Data Center Hardware IPs

, physical design). Analysis and modeling: Creating power models and scripts for performance/power trade-offs. Methodology... or Perl) to enhance power analysis efficiency. Collaboration: Working with other teams, including RTL, Architecture, Physical...

Posted Date: 26 Nov 2025

Physical Design Methodology Engineer

, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve... first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The...

Posted Date: 08 Nov 2025

Senior Digital Design Engineer

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role... the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. Craft...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Jan 2026

Senior Staff Physical Verification CAD engineer - EDA Tools

and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team. The ideal candidate will have a deep... into an efficient and cohesive design flow, ensuring seamless interoperability and maximizing design productivity. Methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 04 Dec 2025
Salary: $124420 - 186400 per year

Senior ASIC Timing Engineer

Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great... human inventiveness and intelligence. What you'll be doing: Drive Timing Analysis and Closure: Lead the timing analysis...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Jan 2026

Senior Principal Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance... Expect As a senior leader in the central physical design team, you will: Shape the long-term vision for physical design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance.... What You Can Expect You will work with a global team on both the physical design of complex chips as well as the methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Senior Staff Engineer, Physical Design

designs utilizing a digital design environment. Good understanding of RTL to GDS flows and methodology Good scripting... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year