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Keywords: EDA Flow Engineer, Location: Santa Clara, CA

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EDA Flow Engineer

Engineering, Computer Science, or equivalent industry experience 2+ years of experience in CAD/EDA flow engineering, design...Work closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 06 Feb 2026
Salary: $110000 - 145000 per year

Senior Solution Engineer - Keysight EDA

. Learn more Keysight Technologies is a leading supplier of Electronic Design Automation (EDA) software for communications... product design. Keysight EDA provides advanced EDA tools for electronic communication and semiconductor manufacturers, chip...

Posted Date: 11 Feb 2026

Senior Staff Physical Verification CAD engineer - EDA Tools

and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team. The ideal candidate will have a deep... for DRC and LVS debugging to streamline physical verification flow. Automate and support physical verification flow...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 04 Dec 2025
Salary: $124420 - 186400 per year

Senior Physical Design Methodology Engineer, Innovus Flows

engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA... technology, EDA tools, and PD flows through collaboration with RTL, synthesis, DFT, foundry, timing other cross functional teams...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Senior Custom CAD Engineer – Flow Development

NVIDIA is seeking a highly motivated and talented CAD Engineer to join our Advanced Technologies group, focusing... with macro validation flows and release processes. Familiarity with ICV decks, Thunder utilities, and EDA tool integration...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Jan 2026

Signoff Methodology Engineer - New College Grad 2026

, to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi.... What You'll Be Doing: Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Feb 2026
Salary: $116000 - 189750 per year

Senior Staff Engineer, Static Timing Analysis (STA) Engineer

Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer, Static Timing Analysis (STA) Engineer... and wireless infrastructure—using the latest technology nodes.Our team leverages cutting-edge EDA tools to solve complex challenges...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Feb 2026
Salary: $131010 - 196300 per year

Senior RTL Analysis Methodology Engineer

Engineer to join our Logic Design Implementation team. The team develops and supports static RTL verification methodologies.... What you'll be doing: Evaluate new EDA tools and features and advance static verification methodologies. Contribute...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Jan 2026

Senior Timing Methodology Engineer

, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive.... What You'll Be Doing: Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Implementation Methodology Engineer - GPU

, formal-equivalence-checking), flow automation and application support. Use NVIDIA implementation flows and EDA tool...We are looking for an Implementation Methodology Engineer to join NVIDIA VLSI team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Senior Staff Optical Engineer, Validation

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Senior Staff Optical Engineer... and support of next generation photonics design flow and design automation. You will be required to provide technical leadership...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Jan 2026
Salary: $130740 - 195800 per year

Senior Physical Design Methodology Engineer

Senior Physical Design Methodology Engineer to solve challenging problems for the next generation technology... that are needed for NVIDIA chips. Participate in developing flow and tool methodologies for chip floorplan, power and clock distribution, chip...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Senior ASIC Physical Design Engineer, Netlisting

, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer... at either block or full-chip level, at project execution and/or flow development. Strong experience in full-chip/sub-chip Static...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 09 Jan 2026

Senior Staff CAD Engineer

Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools... to ever-increasing design challenges Keep up with process and tool evolutions Interface with EDA vendors for optimal tool usage...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Feb 2026
Salary: $127630 - 191200 per year

ASIC Methodology Engineer

technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools... design flow Where you will be working - this role requires the candidate to be onsite in San Diego or Santa Clara...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 13 Feb 2026

Design Engineer - Sensors

tools. Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks... is a plus Experience with C++/SystemC is a plus Experience with High Level Synthesis is a plus Familiarity with MBIST and DFT flow Gate...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Senior ASIC RTL Design Engineer

. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow...

Posted Date: 26 Dec 2025

Senior Principal Engineer, Physical Design

understanding of current design technologies used in major foundries Strong understanding of ASIC design flow, RTL integration..., synthesis, and timing closure In-depth knowledge of modern EDA tools and flows Proficient in automation and scripting using...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior Implementation Methodology Engineer

for all aspects of front-end design implementation methodologies (synthesis, formal-equivalence-checking), flow automation... and application support. Use NVIDIA implementation flows and EDA tool expertise to improve power, performance and area on NVIDIA...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 05 Dec 2025